Loading profile…
Loading profile…
Senior FPGA Engineer
I build and verify FPGA, ASIC, and high-speed hardware for radios, aerospace, networking, and test systems.
CanadaSenior FPGA Engineer at Edgewater Computing System Inc
Restored Linux-based development environment and debugged RTL for MIL-STD-1553 modem project, including issues with inferred memories and DSP rewrites.
FPGARTLLinuxCVSMIL STD 1553 Communication ProtocolPolarFire
Integrated packet switch into Intel's PTP design, designed TDD timing modules, and automated pin verification for FPGA frameworks.
FPGAQuartus IIOrCADJESD204BSignal IntegrityPythonTcl
Bachelor of Science in Electrical Engineering with a major in Computer Engineering, completed through a co-op program in 1994.
Bachelor of Science in Electrical Engineering with a major in Computer Engineering, completed through a co-op program in 1994.
Diploma in Pure and Applied Sciences from Collegian Diploma Studies, completed in 1990.
Diploma in Pure and Applied Sciences from Collegian Diploma Studies, completed in 1990.
Completed online courses in SystemVerilog and UVM verification methodologies.
Completed online courses in Data Communication and Network Services via Coursera.
Completed online course in Network Protocol and Architecture covering Ethernet and IPv4 via Coursera.
Completed online courses in 5G and 4G Network Fundamentals via Coursera.
Designed and verified control FPGA for Tridar Aerospace positioning system, including AHB arbiter, DMA, and telemetry algorithms.
FPGAVHDLAHBAXISDC ConstraintsTMRCode Coverage
Reverse engineered legacy FPGA code, implemented clock domain crossing, and cleaned up timing constraints for MAP300 product.
FPGARTLClock Domain CrossingsTiming Constraints (SDC)GitJiraSignalTap
Implemented Ethernet broadcast function in FPGA, verified multicast features with SystemVerilog, and debugged using WireShark.
FPGAEthernetMulticastSystemVerilogUVM MethodologyWireshark
Designed FPGA for full duplex radio and massive MIMO radio, including JESD interfaces and Microblaze processor integration.
FPGAVivadoJESD204BMicroBlazeSPIRTLSchematic Capture
Implemented FPGA modules in VHDL for wireless jammer, including DSP equations and verification environments.
FPGAVHDLDSPsIIR FiltersSystemVerilogUVM Methodology
Implemented digital portion of blast sensor circuit and FPGA, brought product to production.
FPGACircuit DesignPrototypingDebuggingProduction
Designed and verified ASIC modules for low power wireless transceiver, including AGC, RSSI, and sequencer.
ASICVerilogSystemCVerificationLinux
Designed ASIC modules in Verilog for WLAN PHY, wrote automation scripts in Perl and TCL for logic equivalency check.
ASICVerilogPerlTclLogical Equivalence Checking (LEC)
Designed Bluetooth baseband development platform and FPGA firmware/hardware for DDS demo.
FPGAFirmwareHardware DesignBluetoothC
Designed and brought to production Globalstar Baseband Module, leading to over 200 tester sales.
Hardware DesignMixed SignalHigh Speed DigitalQualcomm ASICPCB Layout
Designed FPGA for PC/PCS RF module development interface and supported CDMA cellular phone digital portion.
FPGACDMARadio FrequencyDigital Design
Designed various PCBs including echo canceller, data card, and line card, and wrote procedures for ISO-9000 accreditation.
PCB DesignMotorola DSPRS 232RS 422RS485V.35ECN
Profile sourced from Himalayas.