Ponnitivalasa Manikantha

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VLSI Design Verification Intern

Aspiring RTL Design Engineer focused on VLSI, who optimized RTL timing and designed RISC-V processors.

IndiaVLSI Design Verification Intern at Vertex Electronics

About

At Vertex Electronics, I designed and simulated digital circuits, including SISO shift registers and an FSM, using Verilog HDL. I also optimized RTL with Synopsys Design Compiler, reducing negative slack from −10 ns to 2 ns. I debugged ChipTop ASIC RTL, resolved design errors, and analyzed timing reports to address setup and hold violations. My work focused on reducing negative slack and improving timing performance. In my RISC-V and UART projects, I designed processor and controller modules, developed testbenches, and verified functionality with RTL simulation. I also developed an obstacle-avoiding robot during my internship at YHills Edutech.

Experience

VLSI Design Verification Intern
Designed and simulated digital circuits including SISO shift registers and FSMs using Verilog HDL. Optimized RTL to reduce negative slack from -10 ns to 2 ns using Synopsys Design Compiler and debugged ChipTop ASIC RTL to resolve design errors and timing violations.
VerilogRTL DesignFunctional ModelingDesign CompilerStatic Timing AnalysisASIC DesignDebugging
Embedded Systems Intern
Developed an autonomous obstacle-avoiding robot using Arduino UNO and an ultrasonic sensor. Programmed the robot in Embedded C to detect obstacles and automatically change direction, integrating sensor with motor control for real-time navigation.
ArduinoEmbedded CUltrasonic SensorsMotor ControlRobotics

Education

GIET University
Pursuing a Bachelor of Technology in Electronics and Communication Engineering with a specialization in VLSI, maintaining a CGPA of 8.70.
Maharshi Gurukul - CHSE
Completed Intermediate in Science with MPC, achieving a percentage of 77%.
Vidyaniketan Public School
Completed Matriculation under CBSE with a percentage of 76%.

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About

Experience

VLSI Design Verification Intern

Designed and simulated digital circuits including SISO shift registers and FSMs using Verilog HDL. Optimized RTL to reduce negative slack from -10 ns to 2 ns using Synopsys Design Compiler and debugged ChipTop ASIC RTL to resolve design errors and timing violations.

VerilogRTL DesignFunctional ModelingDesign CompilerStatic Timing AnalysisASIC DesignDebugging

Embedded Systems Intern

Developed an autonomous obstacle-avoiding robot using Arduino UNO and an ultrasonic sensor. Programmed the robot in Embedded C to detect obstacles and automatically change direction, integrating sensor with motor control for real-time navigation.

ArduinoEmbedded CUltrasonic SensorsMotor ControlRobotics

Education

GIET University

Pursuing a Bachelor of Technology in Electronics and Communication Engineering with a specialization in VLSI, maintaining a CGPA of 8.70.

Maharshi Gurukul - CHSE

Completed Intermediate in Science with MPC, achieving a percentage of 77%.

Vidyaniketan Public School

Completed Matriculation under CBSE with a percentage of 76%.

About

Experience

VLSI Design Verification Intern

Embedded Systems Intern

Education

GIET University

Maharshi Gurukul - CHSE

Vidyaniketan Public School

About

Experience

VLSI Design Verification Intern

Embedded Systems Intern

Education

GIET University

Maharshi Gurukul - CHSE

Vidyaniketan Public School

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