SAIPRASAD ARALE

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Design Verification Intern

Embedded systems and design verification engineer developing Verilog adder architectures and Arduino-based automation projects.

IndiaDesign Verification Intern at Master VLSI

About

At Master VLSI, I developed functional test cases and verified simulation waveforms using Verilog, SystemVerilog, EDAPlayground, and QuestaSim. I also worked with verification flows for AMBA protocols, including APB, AHB, and AXI. For my Kogge-Stone and Brent-Kung adder project, I developed Verilog architectures for digital image processing sub-modules and analyzed their timing, area, and power characteristics. I built a sun-tracking solar panel project using Arduino, dual LDR sensors, and Embedded C to adjust the panel based on sunlight intensity. I also created a water-level controller that used ultrasonic sensor readings and relay modules to control a pump. As a part-time Technician at Tejas Networks Pvt Ltd, I repaired PCBs and replaced components on telecom hardware. I diagnosed faults using multimeters and other debugging instrumentation.

Experience

Design Verification Intern
Acquired expertise in Verilog, SystemVerilog, and digital electronics to author robust designs and testbenches. Developed custom functional test cases and verified complex simulation waveforms using EDAPlayground and Questasim.
VerilogRTL DesignTestBench DevelopmentCombinational And Sequential Circuits DesignStatic Timing AnalysisPower AnalysisArea OptimizationXilinx Vivado
Technician (Part-time)
Executed precision PCB repair and component replacement on telecom hardware architecture, enhancing device reliability. Diagnosed hardware faults using testing tools and standard troubleshooting techniques, improving repair efficiency.
PCB DiagnosticsCapacitor ReplacementSoldering and Desolderingmultimeter

Education

JSS Academy of Technical Education
Pursuing a Bachelor of Engineering in Electronics and Communication Engineering with a CGPA of 7.75/10.
SC Gurukula PU College
Completed Pre-University Course with a percentage of 85.16%.
SC Gurukula Presidential High School
Completed Secondary School Leaving Certificate with a percentage of 92.96%.

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About

Experience

Design Verification Intern

Acquired expertise in Verilog, SystemVerilog, and digital electronics to author robust designs and testbenches. Developed custom functional test cases and verified complex simulation waveforms using EDAPlayground and Questasim.

VerilogRTL DesignTestBench DevelopmentCombinational And Sequential Circuits DesignStatic Timing AnalysisPower AnalysisArea OptimizationXilinx Vivado

Technician (Part-time)

Executed precision PCB repair and component replacement on telecom hardware architecture, enhancing device reliability. Diagnosed hardware faults using testing tools and standard troubleshooting techniques, improving repair efficiency.

PCB DiagnosticsCapacitor ReplacementSoldering and Desolderingmultimeter

Education

JSS Academy of Technical Education

Pursuing a Bachelor of Engineering in Electronics and Communication Engineering with a CGPA of 7.75/10.

SC Gurukula PU College

Completed Pre-University Course with a percentage of 85.16%.

SC Gurukula Presidential High School

Completed Secondary School Leaving Certificate with a percentage of 92.96%.

About

Experience

Design Verification Intern

Technician (Part-time)

Education

JSS Academy of Technical Education

SC Gurukula PU College

SC Gurukula Presidential High School

About

Experience

Design Verification Intern

Technician (Part-time)

Education

JSS Academy of Technical Education

SC Gurukula PU College

SC Gurukula Presidential High School

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